FIELD OF THE INVENTION
The present invention relates to a gate array type semiconductor integrated circuit.
FIG. 17 is a plan view showing a basic cell structure of a prior art gate array type semiconductor integrated circuit. As shown in FIG. 17, each of basic cells 1 is comprised of a pair of transistors, a PMOS transistor TP and an NMOS transistor TN.
The PMOS transistor TP is made by forming a PMOS transistor gate 12 on a P.sup.+ diffusion layer 17 while the NMOS transistor TN is made by forming an NMOS transistor gate 13 on an N.sup.+ diffusion layer 18. The PMOS transistor gate 12 and the NMOS transistor gate 13 are electrically connected to each other by a connection pin 15. Reference numerals 11, 14 and 16 designate a power source, a ground and an insulating oxide film, respectively.
FIG. 18 is a sectional view taken along the line II--II of FIG. 17. As shown in FIG. 18, the PMOS transistor gate 12 is selectively formed on a semiconductor substrate 51, and an insulating film 53 is formed on the PMOS transistor gate 12 except for part of it. Then, the connection pin 15 is formed covering part of the insulating film 53 and the PMOS transistor gate 12 on which no portion of the insulating film 53 lies.
Then, as shown in FIG. 19, the basic cells 1 are arranged in cell alignments 3 on a chip 5 and the cell alignments 3 are arranged in array with wiring regions 31 defined between adjacent ones of the cell alignments 3 to constitute a gate array type semiconductor integrated circuit. Reference numeral 6 designates input/output buffers, and reference numeral 7 designates bonding pads.
Also, as shown in FIG. 20, a dense array of the basic cells 1 on the chip 5 constitute a gate array type semiconductor integrated circuit. In such a case, part of the basic cells 1 are used as wiring regions.
A combination of several of the basic cells 1 can constitute a macro cell having a predetermined logic function. For example, an NAND gate 10 receiving signals on input terminals A, B and C as shown in FIG. 21 consists of three PMOS transistors T1 to T3 and three NMOS transistors T4 to T6, as shown in FIG. 22.
Thus, as shown in FIG. 23, via-holes (marked with "x" in FIG. 23) are provided in predetermined points, and wiring L1 is provided between the basic cells 1, so that the NAND gate 10 shown in FIG. 21 working as a macro cell 2 can be implemented.
A length of exemplary one of the basic cells 1 shown in FIG. 17 is equal to one-wiring pitch W1 determined by a minimum wiring interval in the semiconductor manufacturing technology. In this way, as shown in FIG. 24, the basic cells 1 are arranged in row to constitute the cell alignments 3. Thus, intervals between adjacent ones of connection pins 15 in any of the cell alignments 3 are also all equal to the single wiring pitch W1. The connection pins 15 of the basic cells 1 in any of the cell alignments 3 and their respective counterparts of the basic cells 1 in the adjacent cell alignment, opposed to each other, all lie in the same X coordinates, assuming herein that the cells are aligned in X-direction.
Adjacent ones of the cell alignments 3 define the wiring regions 31, and external wirings are provided between the separate basic cells 1, especially between the basic cells 1 in the separate cell alignments 3 by providing wirings in the wiring regions 31. The external wirings provided in the wiring regions 31 are usually of dual-layer system where one layer is used for lateral wiring (wiring in the X-direction) while the other layer is used for longitudinal wiring (wiring in Y-direction perpendicular to the X-direction). Electrical connection of the lateral wiring with the longitudinal wiring is established by forming via-holes in positions where both the wirings overlap with each other. For wiring layers where the wirings are provided, metal layers of aluminum, gold or the like are often used, and polysilicon layers may be used.
In the prior art gate array, the basic cells 1 are configured and arranged in the afore-mentioned manner, and the lateral wiring and longitudinal wiring are provided in the wiring regions 31 for connections between the basic cells 1 formed in the separate cell alignments 3.
Thus, there arises the problem that relative positions in wiring patterns of the lateral and longitudinal wirings are restricted (referred to as "wiring restrictions" hereinafter).
For example, as shown in FIG. 25, in case where first wiring electrically connecting a basic cell 1A in a cell alignment 3A and a basic cell 1C in a cell alignment 3B and second wiring electrically connecting a basic cell 1B in the cell alignment 3A and a basic cell 1D in the cell alignment 3B are to be formed in the wiring region 31 defined between the cell alignments, longitudinal wiring 42A, lateral wiring 41A and longitudinal wiring 42C are used for the first wiring while a longitudinal wiring 42B, lateral wiring 41B and longitudinal wiring 42D are used for the second wiring.
In this case, since the basic cells 1C and 1D respectively take positions one cell aside from counterparts of the basic cells 1A and 1B in the X-direction, a wiring restriction that the lateral wiring 41A in the first wiring should be positioned lower than the lateral wiring 41B in the second wiring in the Y-direction is imposed.
Additionally, as shown in FIG. 26, in case where cross wiring is to be provided, that is, first wiring electrically connecting a basic cell 1A in a cell alignment 3A and a basic cell 1D in a cell alignment 3B and second wiring electrically connecting a basic cell 1B in the cell alignment 3A and a basic cell 1C in the cell alignment 3B are to be formed, an illogical wiring restriction that lateral wiring 41A in the first wiring should be formed at once upper and lower than the lateral wiring 41B in the second wiring in the Y-direction is imposed, and thus, there arises the problem that the first and second wiring cannot be appropriately formed in the wiring region 31.
For that reason, it is needed that the lateral wiring of one of the first and second wirings be divided in connecting the associated cells, or that a bypass wiring be formed by using other wiring regions.
Because of the wiring restrictions as mentioned above, the external wiring between the basic cells 1 becomes more complicated as numerous numbers of the basic cells 1 are used for logic circuits to be constructed in the prior art gate array type semiconductor integrated circuit, and there arises the problem that a tremendously long processing time is required to provide the external wiring so as to satisfy the wiring restrictions even with automatic designing by a computer. Worst of all, wiring is impossible.